Secure Hierarchy-Aware Cache Replacement Policy (SHARP)

Secure Hierarchy-Aware Cache Replacement Policy (SHARP)

In cache-based side channel attacks, a spy that shares a cache with a victim probes cache locations to extract information on the victim’s access patterns. For example, in evict+reload, the spy repeatedly evicts and then reloads a probe address, checking if the victim has accessed the address in between the two operations. While there are many proposals to combat these cache attacks, they all h...

A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors

Chip multiprocessors (CMPs) usually employ shared, lastlevel caches to use on-chip memory resources effectively. Unfortunately, conventional replacement policies applied to shared caches fail to partition memory resources among cores to achieve an optimal execution throughput. This paper presents a novel replacement policy that dynamically estimates how many misses would be eliminated if one mo...

Popularity-Aware Cache Replacement in Streaming Environments

DRAM-Aware Last-Level Cache Replacement

The cost of last-level cache misses and evictions depend significantly on three major performance-related characteristics of DRAM-based main memory systems: bank-level parallelism, row buffer locality, and write-caused interference. Bank-level parallelism and row buffer locality introduce different latency costs for the processor to service misses: parallel or serial, fast or slow. Write-caused...

MadCache: A PC-aware Cache Insertion Policy

While the field of computer architecture is always looking for novel research directions to bring improved performance and efficiency, it is often simple improvements to more mature topics that have the most substantial impact. Cache replacement policy is one such research area, where innovations are highly sought after because of their direct improvement on performance. Furthermore, as chip-mu...